Rapidly increasing power consumption in SOCs demand aggressive power saving techniques. Static power chain designs are overdesigned with excessive margins. This reduces the effectiveness of any dynamic power saving strategy.
Traditionally, designs have been very conservative on power grid design using higher margins than those needed for safe operation. This is especially true for process-driver designs which may not have enough data on process characteristics.
A traditional power chain design connects the power switches in a serial fashion. This restricts the power sequence duration to a single value. Usually this value is determined considering the worst case scenarios of maximum activity such as the maximum number of modules powering up/down together.